1. Field of the Invention
The present invention relates to recovery of cached data from a malfunctioning CPU; and, more particularly, to a technique for disabling a malfunctioning CPU while recovering the data stored in the cache of the CPU in a large scale, multiprocessor computer system.
2. Description of Related Art
Large scale data processing systems, such as those operating in accordance with the IBM ESA/390 architecture, include a plurality of central processing units. Each central processing unit includes a cache which stores data which may have been modified by the CPU. When a particular CPU malfunctions, the CPU must be stopped; data must be recovered from the cache, and then the system must be reconfigured to disable the CPU until it can be repaired or replaced.
In one type of computer system, the cache memory associated with the CPU is referred to as a "store-to" cache. A store-to cache may store lines of data that have been modified by the local CPU, but have not yet been copied back to mainstore. Thus, the cache may hold the only valid, current copy of a line of data. In order to disable a CPU which includes a store-to cache, it is critical to data integrity of the overall system to be able to recover the modified lines of data from the malfunctioning CPU.
Prior art techniques involve recovery of the cached data using the hardware of the CPU which is malfunctioning. This creates the risks that the malfunctioning CPU hardware will cause errors in the data that cannot be corrected or may not be able to recover the data at all.
Therefore, it is desirable to accomplish the disabling of a malfunctioning CPU, while recovering modified lines of data from the CPU, without reliance on the malfunctioning CPU hardware to deliver the modified data.